The present invention relates to improved means and methods for simulating the design and operation of computer logical circuitry.
In recent years, various apparatus and methods have been developed for the purpose of aiding an engineer in the design evaluation and simulation of logical circuitry, such as illustrated for example, in U.S. Pat. No. 4,583,169 and U.S. Pat. No. 4,590,581. However, such approaches do not significantly relieve the heavy burden on the design engineer in designing, simulating and evaluating computer logical circuitry.
An approach which goes significantly further in aiding the design engineer is exemplified by computer-aided engineering systems wherein an engineer is aided in the design of logical circuitry by interacting with a display terminal controlled by the computer. Systems of this type also tyically provide for a software simulation of the designed logical circuits so that their performance can be tested without having to build the actual hardware. A typical computer aided design (CAD) system currently in use is the Mentor IDEA 1000 system commercially available from Mentor Graphics Corporation, Newport Beach, Calif.
The Mentor system provides for the creation by an engineer, using highly sophisticated graphic aids, of a "bottom-up" software representation of a desired logical circuit design whereby "macrocells" form the lowest level in the design structure. In a typical Mentor system up to 440 different macrocells based on MCA2500ECL technology are available for use in designing logical circuits such as, for example, the logical circuits to be provided for a gate array. Using Mentor, an engineer would design logical circuitry for a gate array by interconnecting the inputs and outputs of particular selected ones of these macrocells to provide the various logical functions desired for the array. The Mentor system permits this to be accomplished much more conveniently and expeditiously than would be possible if this were done in the old way, by hand, or by using the teachings of the aforementioned U.S. Pat. No. 4,583,169.
The resulting design connectivity information for the circuitry being designed (for example, a gate array) is stored in the Mentor design data base. Mentor also provides for storage of a Macrocell Library which defines the logical operations provided by each macrocell. Together, these constitute a "bottom-up" software representation of the logical circuitry designed by the engineer using the Mentor system. The Mentor system also provides for simulating the operation of logical circuitry using such a "bottom-up" software representation. However, only a relatively slow simulation is possible using this "bottom-up" software representation because of the relatively large number of processing operations which such a representation requires be performed in order to simulate the required logical functions. This problem is particularly severe where simulation is to be performed for a large number of interconnected Mentor-created logical circuits. As is well known, a slow simulation capability can seriously hamper the development of computer logical circuitry.